1. Field of the Invention
The present invention relates to a method of manufacturing a semiconductor device, in particular, to a process of CMP (Chemical Mechanical Planarization) for forming a Cu damascene wiring, etc. of a high-velocity LOGIC-LSI.
2. Description of the Related Art
It is expected that the integration of semiconductor elements in high performance LSIs of the next generation would be inevitably further enhanced. For example, the design rule of damascene wirings to be formed by CMP is expected to become so severe that the line width of wirings is confined within the range of 0.07 to 30 μm and the film thickness of wirings is confined to 100 nm for example.
In the formation of damascene wirings having a film thickness of 100 nm for example, the CMP employing a slurry is generally adopted. Due to this CMP, the residues of shavings and components of slurry adhere to the surface of semiconductor device or of the polishing pad. Although most of these residues can be washed away by polishing using deionized water (DIW), it is difficult to sufficiently remove the oxides deposited on the surface of Cu wiring or the Cu compounds left remained on the polishing pad by deionized water. Therefore, in order to remove these Cu oxides and Cu compounds, it is required to perform chemical-polishing using an exclusive chemical solution comprising, as a major component, ammonia, inorganic acid such as hydrochloric acid, or organic acid such as citric acid.
If the polishing using such a chemical solution is to be performed, it is required to additionally prepare an installation dedicated to the chemical solution. Moreover, there is a risk of generating the corrosion of Cu due to the mixing of the chemical solution with the slurry. On the other hand, there are also noticed problems such as the generation of dust or scratches during the chemical-polishing or the generation of cracks of low-k film having a relative dielectric constant of 2.9 or less.
At present however, no one has succeeded in developing a manufacturing method of a semiconductor device which is capable of obviating the generation of these defects to obtain a semiconductor device of high reliability.